1. Field of the Invention
This present invention relates to semiconductor chips and their alignment and fixing to another chip or substrate. The invention relates specifically to a method and apparatus for gracefully degrading performance of a proximity communication channel in response to misalignment of one or more semiconductor chips.
2. Related Art
Proximity communication (PxC) is a well known technology that enables communication between two integrated circuit chips, but that also relies upon face-to-face alignment of those chips, as has been explained by Drost et al. in “Proximity Communication,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, September 2004, pp. 1529-1535. Misalignment between these two chips between which the proximity communication channel is formed may occur for a number of reasons, including but not limited to: inaccurate placement in a package or on a printed circuit board (PCB) or other carrier substrate; temperature variations leading to thermal expansion or contraction; or mechanical displacement, including stress deformation or vibration. Any misalignment between chips will reduce the effectiveness of face-to-face proximity communication, whether that communication is moderated through capacitive coupling, inductive coupling, optical coupling, or a direct conductive path.
Methods have been described in the prior art for automatically detecting and correcting for this misalignment, such as U.S. Published Patent Application 2007/0266557 to Drost et al. The misalignment detection uses a mechanism for determining chip position and is not covered here. Also, the prior art teaches how to automatically correct for misalignment, using piezo-electric, electro-static, electro-thermal, or inductive actuators to adjust the chips, such as U.S. Published Patent Application 2004/0227221 to Harris et al. Although such actuators may be effective in some situations to correct misalignment, they are often difficult and expensive to implement.
However, the prior art has failed to teach a method of gracefully degrading the link performance in response to chip misalignment without necessarily realigning the chips. This degradation may take the form of slowing down the data rate of the channel, increasing the latency in the channel, or increasing the power used by the channel.